Sadrieh, Arash and Charissis, Stefan and Hill, Adam P (2013) An On-chip Heterogeneous Implementation of a General Sparse Linear Solver. Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International. pp.54-63. ISSN 978-0-7695-4979-8 (OA)
Full text not available from this repository.Abstract
Inter-device communication is a common limitation of GPGPU computing methods. The on-chip heterogeneous architecture of a recent class of accelerated processing units (APUs), that combine programmable CPU and GPU cores on the same die, presents an opportunity to address this problem. Here we describe an APU-based heterogeneous implementation of the Jacobi-preconditioned conjugate gradient method and identify a set of optimal configurations based on examination of standard matrices. By leveraging the low-latency memory transactions of the APU and exploiting CPU/GPU cohabitation for concurrent vector operations, a comparable performance to that of a high-end GPU running CUSP is achieved. Our results show that use of on-chip heterogeneous architectures can be attractively cost-effective and even show better performance for applications with a low number of linear solver iterations and when device-to-device data transfer is significant. Accordingly, the APU architecture and associated GPAPU methods have significant potential as a low cost, energy efficient alternative for parallel HPC architectures.
(NHMRC 1006016)
| Item Type: | Article |
|---|---|
| Subjects: | R Medicine > R Medicine (General) |
| Depositing User: | Repository Administrator |
| Date Deposited: | 28 Jan 2016 03:18 |
| Last Modified: | 28 Jan 2016 03:18 |
| URI: | https://eprints.victorchang.edu.au/id/eprint/256 |
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